1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a dual gate oxide in a dual voltage process.
2) Description of the Prior Art
Modem integrated circuit devices commonly contain transistors and other circuit elements that operate at differing voltage levels. For example, integrated circuit devices that contain non-volatile memories usually contain both high and low voltage circuit elements. Such non-volatile memories typically include circuit elements that operate at relatively high voltage levels for program and erase operations as well as other circuit elements that operate at relatively low voltage levels.
High voltage circuit elements such as program and erase transistors are usually formed over a semiconductor substrate, or wafer, on a relatively thick gate oxide layer. Such relatively thick gate oxide layers are required to prevent breakdown in a high voltage operating environment. However, it is preferable for the low voltage circuit elements to be formed on a relatively thin gate oxide layer. Such thin gate oxide layers typically increase the speed of such circuit elements. For example, transistors having relatively short gate lengths and thin oxide layers typically provide increased operating speeds.
To accommodate the need for circuit elements which must operate at different voltages, modern integrated circuits are commonly fabricated using a dual gate oxide (e.g. a gate oxide layer having two different thicknesses) or multiple gate oxide thicknesses. One approach to fabrication of a gate oxide layer having multiple thicknesses involves multiple masking and oxide formation steps. Typically, a first oxide sublayer is grown on the semiconductor substrate. The first oxide sublayer is usually masked with a photoresist mask and the unmasked portions of the first oxide sublayer are stripped away in the area where a thin oxide layer is desired. The photoresist mask is then stripped away and a second oxide sublayer is grown on the semiconductor substrate to form thin oxide areas, and on the first oxide sublayer to form thick oxide areas. However, the photoresist mask is difficult to remove completely, and photoresist residue reduces the overall quality of the subsequently formed second oxide sublayer.
Another approach to fabrication of a gate oxide layer having multiple thicknesses is to grow an oxide layer having the greater off the desired thicknesses. Then masking the areas where a thick oxide is desired using a photoresist mask, and etching the exposed areas of the oxide layer to the thinner of the desired thicknesses. However, it is difficult to control the thickness of the etched areas of the oxide layer, hindering the performance and reliability of the device formed on the thin oxide areas.
Yet another approach to fabrication of a gate oxide layer having multiple thicknesses is to implant N-type ions which enhance oxide growth and nitrogen ions which retard oxide growth. A first implant mask is formed over the semiconductor substrate having openings over areas where a second oxide thickness is desired, and N-type ions are implanted into the semiconductor substrate through the openings. The implant mask is removed, and the N-type ions are driven in with a thermal anneal. A second implant mask is formed having openings over areas where a first oxide thickness and a second oxide thickness are desired, and nitrogen ions are implanted into the semiconductor substrate through the openings in the second implant mask. An oxide layer is then grown having a first thickness where only nitrogen ions have been implanted, a second thickness where both N-type and nitrogen ions have been implanted, and a third thickess where no ions have been implanted. While this process is benificial in applications where an N-type doped region is desired beneath a second thickness oxide, such a doped region is not desirable in some applications, such as dual voltage devices and multiple voltage devices. Also, this process requires separate masking steps and a thermal anneal, increasing the thermal budget, cycle time, and fabrication costs.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,672,521 (Barson et al.) shows a multiple thickness oxide layer formed by implanting nitrogen ions into a semiconductor substrate to retard oxide growth with or without N-type ions to enhance oxide growth to make varing thicknesses of relatively thin oxide, and using undoped areas of the semiconductor substrate to grow relatively thick oxide.
U.S. Pat. No. 5,918,116 (Chittipeddi) shows a dual gate oxide process by an amorphizing ion implant, preferably silicon.
U.S. Pat. No. 5,624,866 (Kim) shows an ion implant to enhance oxide growth wherein argon is one of several suitable ion species.
U.S. Pat. No. 4,597,164 (Havermann teaches a dual oxide method by doping a thick oxide area.
U.S. Pat. No. 5,668,035 (Fang et al.) shows a dual thickness gate oxide process by a masking step.
U.S. Pat. No. 5,330,920 (Soleimani et al.) and U.S. Pat. No. 5,891,798 (Doyle et al.) teach a gate oxide method by nitridizing or implanting N2 ions into a semiconductor substrate.
U.S. Pat. No. 5,866,445 (Baumann) shows a dual gate oxide thickness using a N2 ion implant.
It is an object of the present invention to provide a method for forming a dual thickness gate oxide using a nitrogen ion implant to retard oxide growth in a first area and an argon ion implant to enhance oxide growth in a second area.
It is another object of the present invention to provide a method for forming a multiple thickness gate oxide using a nitrogen ion implant to retard oxide growth in a first area to provide a first thickness, using an argon ion implant to enhance oxide growth in a second area to provide a second thickness, and using an undoped third area provide a third thickness in a subsequently grown oxide layer.
It is yet another object of the present invention to provide a method for forming a multiple thickness gate oxide with reduced thermal budget and reduced processing steps by using a nitrogen ion implant to retard oxide growth in a first area and an argon ion implant to enhance oxide growth in a second area, with or without an third area.
To accomplish the above objectives, the present invention provides a method for forming a multiple thickness gate oxide layer. The process begins by providing a semiconductor substrate having a silicon surface. The semiconductor substrate has a first area and a second area, and may further comprise an optional third area. Nitrogen ions into the first area while masking the second area and the third area to form a first region in which thermal oxide growth is retarded. Argon ions are implanted into the so area while masking the first area and the third area to form a second region in which thermal oxide growth is enhanced. A gate oxide layer is thermally grown over the first region, the second region, and the third region; wherein the gate oxide layer has a first thickness over the first region, a second thickness over the second region, and a third thickness in the third area. The second thickness is greater than the first thickness and the third thickness, and the third thickness is greater than the first thickness.
The present invention provides considerable improvement over the prior art. The key advantages of the present invention are that a multiple thickness gate oxide layer can be formed using an easily manufacturable single oxide growth process with a reduced thermal budget and reduced processing steps. The thick area is not doped with N-type ions. Also, since the thin gate is grown at the same time as the thick gate in a single oxidation step, boron is not lost from the thin gate area during the first (thick gate) oxidation step, and a compensation implant is not needed.
Another key advantage is that a threshhold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argon implant for a high voltage gate, further reducing processing steps.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.